The present invention generally relates to semiconductor device manufacturing, and more particularly to trench patterning using a block first sidewall image transfer technique.
Semiconductor device manufacturing generally includes various steps including a patterning process. For example, the manufacturing of a semiconductor chip may start with, for example, CAD (computer aided design) generated device patterns and may continue with the effort to replicate these device patterns in a substrate in which semiconductor devices can be formed. The replication process may involve the use of a photolithography process in which a layer of photo-resist material may be first applied on top of a substrate, and then be selectively exposed according to a pre-determined device pattern. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to a certain solution. Next, the photo-resist may be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern. The photo-resist pattern may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
Engineers are continuously facing the challenge of how to meet the market demand for ever increasing device density. One technique for tight pitch patterning is to achieve twice the pattern density through a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer. A conventional block last SIT process can include lithographically forming a mandrel above a substrate from a suitable photo-resist material. A material suitable for forming spacers is subsequently deposited on top of the mandrel and to eventually form spacers next to the mandrels. The mandrel can then be removed and the remaining spacers can defined the desired device pattern. Next, a block mask litho step may be applied to remove a portion of the device pattern formed by the spacers. The block mask litho step may be designed to define a pattern region of the structure, and thus ensure only a portion of the device pattern within the pattern region is transferred to underlying layers and eventually the substrate. Lastly, the device pattern may be transferred into an underlying substrate, again, only within the pattern region defined by the block mask litho step.
However, concerns and issues have been observed in the above block last SIT process. Accordingly it may be advantageous to make changes to the current fabrication techniques to address the deficiencies described above.